Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional current mirror. The current mirror circuit 100 is generally employed to mirror an accurate input current IIN for an external circuit 104 that has a desired minimum accuracy. To accomplish this, current mirror circuit 100 employs a pair 102 of cascoded drain extended (DE) NMOS transistors Q1 and Q2. These transistors Q1 and Q2 are coupled to the drains of the current mirror (which is generally comprised of NMOS transistors Q3 and Q4).
A problem with this circuit results from the bulk leakage currents of the DE NMOS transistors Q1 and Q2. In operation, the input current IIN is generally the sum of current through transistor Q1 or I1 and the bulk leakage current I2 of transistor Q1. The current I1 is mirrored, while current I2 is not. Instead, transistor Q2 has a bulk leakage current I4, which may not be the same as current I2. This results in the output current being approximately equal to the sum of current I1 and current I4, which is not necessarily equal to the input current IIN. Generally, this output current is IIn+I4−I2. Thus, there are inaccuracies in the mirrored current due to the deleterious effects of bulk leakage currents.
Some other examples of conventional circuits are PCT Publ. No. WO/2006034371; and U.S. Patent Pre-Grant Publ. Nos. 2008/0191802; 2008/0258826; and 2009/0015329.